1. Field of the Invention
The invention generally relates to a semiconductor memory having a short effective word line cycle time and a method for reading data from a semiconductor memory.
2. Description of the Related Art
Besides its storage capacity and integration density, one of the most important properties of a semiconductor memory is the effective time needed to access its memory cell array in the case of a random access operation. Such an access time that is as short as possible for a random access operation is particularly important in network applications, in particular. The access time for randomly accessing the cell array of the semiconductor memory is often also referred to as the word line cycle time tRC (or row cycle time) and represents the minimum time between two operations of randomly accessing the cell array of the semiconductor memory.
FIG. 2 shows a simplified schematic timing diagram for illustrating the word line cycle time tRC. The clock signal is schematically illustrated in the horizontal direction in the top region of FIG. 2. A read command “Cmd Read” is applied to the (conventional) semiconductor memory on a particular rising edge of the clock signal. The read command “Read” relates to the bank address “BA0”. The data “Data” which have been read from the memory bank are available at the data output of the semiconductor memory after a certain delay or latency. In order to read the data “Data” associated with the given bank address “BA0” from the semiconductor memory, a relevant word line of the memory bank is conventionally “opened” in order to read the data contents of the at least one memory cell via the associated bit line(s). However, in the event of a new operation of completely randomly accessing the memory bank (complete random access), it is generally necessary to open a different word line in the case of a read command, the word line which is already open having to be closed beforehand. In the worst-case scenario, a complete so-called word line cycle which has a cycle duration of tRC must thus be carried out for an operation of completely randomly accessing the memory bank. In the worst-case scenario, the memory bank cannot be accessed again until after this word line cycle time has elapsed.
The prior art discloses a number of concepts for shortening the access time for randomly accessing a memory bank of a semiconductor memory. The increasing importance of fast semiconductor memories, particularly for network applications, has thus, for example, led to the development of a new class of semiconductor memories which are known under the name RLDRAM (Reduced Latency Dynamic Random Access Memory). RLDRAMs combine high storage densities with short word line cycle times tRC. However, even shorter word line cycle times tRC are advantageous for particular applications.
In particular, a concept known as “multibanking” has conventionally been used at the system level for such cases, thus making it possible to “artificially” shorten the effective word line cycle time further. The concept is particularly suited to the case in which the number of read commands to be executed is large in comparison with the number of write commands, for example, in the case of so-called “look-up tables”. The functional principle of such a conventional “multibanking method” for artificially shortening the effective word line cycle time is explained below with reference to FIG. 3. In a similar manner to FIG. 2, the time axis is illustrated in the horizontal direction in FIG. 3, a schematic clock signal being shown in the top region. A read command “Read” is used to address a first memory bank “B0” on a first rising clock edge. As has already been explained in connection with FIG. 2, in the worst-case scenario, a new read command cannot be applied to the first memory bank “B0” until after a word line cycle time tRC of this memory bank, with the result that the access time for the memory bank “B0” is equal to the word line cycle time tRC. In order to nevertheless achieve a shorter effective access time, a specially configured memory controller is used at the system level. The external memory controller is designed in such a manner that it duplicates the data or information of a first memory bank in one or more shadow memory banks. By way of example, the same data or information as in a shadow memory bank “B1” are/is present in the first memory bank “B0”. The memory bank and the shadow memory bank are preferably of identical design.
If, in the case of such a “multibanking method”, another read command is applied to the first memory bank “B0” within the word line cycle time tRC, the memory controller checks whether the so-called “tRC condition” has been satisfied for the memory bank “B0”, that is to say the external memory controller checks whether the first memory bank “B0” is in such a memory state that would not allow the data which are to be read to be read directly. In such a memory state which will be referred to as an “open memory state” below, an open word line must first of all be closed before the new read command can be executed. If such a case is present, that is to say the “tRC condition” has not been satisfied for the first memory bank “B0”, the external memory controller diverts the read command to the shadow memory bank “B1”. Although the read command was thus intended for the memory bank “B0”, the special configuration of the memory controller results in the shadow memory bank “B1” which is not in the open memory bank state being read. This shortens the effective access time or effective word line cycle time tRC,eff by a factor of 2, as is schematically illustrated in FIG. 3. This so-called “multibanking method” may also be carried out using a plurality of duplicated shadow memory banks in order to shorten the effective word line cycle time tRC,eff further in a corresponding manner.
However, the known “multibanking method” has two fundamental disadvantages. On the one hand, the external memory controller must check and log which of the memory banks are in an open memory bank state and should a read command for such an open memory bank be received, plan for the read command to be diverted in the form of a read access operation to a shadow memory bank. Such a process of diverting and logging and planning read access operations to memory banks leads to a high level of complexity of the memory controller/semiconductor memory system and thus complicates the entire system. On the other hand, on account of the prescribed bus architecture, each time data or information are/is to be written to one of the memory banks, a subsequent write command must also be applied to the shadow memory bank or shadow memory banks. The accelerated access time when reading data is thus paid for with an extended write time for writing the data.